Introduction

The S5L8310 provides CD DSP, CD ROM decoding, MP3/WMA Decoding, CD-ESP , the 10 bandequalizer function and the 1-bit DAC function. This IC is designed to support the low power algorithmfor low power consumption, which is most important factor for the portable device, and the hardwareASIC for low operation frequency.

Features

• CD DSP
  • EFM Data Demodulationr
    
  • Frame Sync detection, protection, insertion
    
  • 24 GPIO or Special purpose I/O
    
  • Internal 16K SRAM for De-interleave
    
  • Interpolation
    
  • Digital Audio Interface
    
  • Variable Speed CLV Control (X1 ~ X2)
    
  • CLV/Pseudo-CAV Servo Control
    
  • Wide Capture Range Digital PLL (±50%)
    
  • Sub code Data process
    
  • (Q Data CRC Check, Q Data Register installed)
    
  • Error correction
    
  • (C1 : 2 Error correction, C2 : 4 Erasure correction)
    
    
    
• Digital filter, DAC Part
  
  • 8 times over-sampling Digital Filter
    
  • Digital De-emphasis
    
  • 10 Band EQ
    
  • On chip Sigma-Delta Stereo DAC
    
  • Audio Low Pass Filter
    
    
    
• ESP for CD Audio play (Electrical shock proof)
  
  • Supports 4 bit compression and non-compression mode
    
  • CD ESP Play time with 4 bit compression mode
    
    • 4M DRAM : 10 seconds' ESP
      
    • 16M DRAM : 40 seconds' ESP
      
    • 64M DRAM : 160 seconds' ESP
      
    • 128M DRAM : 320 seconds' ESP
      
      
      
• CD ROM Decoding
  
  • CD-Text Decoding
    
  • CD-ROM Decoding
    
    • Block Sync Detection/Insertion/Protection
      
    • Error Detection Code (EDC)
      
    • Error Correction Code (ECC)
      
• Support repeat correction mode
  
• Video-CD Audio Data Decoder
  
  
  
• MP3 / WMA Decoding
  
  • Single-Chip MPEG 1/ 2 / 2.5 Layer 3 (MP3 Audio Data Decoder)
    
    • ISO/IEC 11172-3(MPEG1 Audio) & ISO/IEC 13818-3.2 (MPEG2 Audio) Layer 3
      
  • Window Media Audio (WMA) Data decoding
    
    • Supports WMA Version 7.0 / 8.0 / 9.0 (except Pro, Voice, VBR)
      
      
      
• Hardware
  
  • Architecture : 0.18 um CMOS Technology
    
  • Operating condition : 16.9344Mhz
    
  • Package : 128 TQFP
    
  • Operating voltage
    
    • Core supply power : 1.1 ~ 1.3v
      
    • I/O supply power : 3.0 ~ 3.6v
      
  • Low power consumption
    
    • Low power dissipation for MP3 decoder :
      
    • Power Off Function : IDLE Mode
      
    • Reduced power management system for each sampling frequency
      
  • Supports diverse DAC I/F Output format
    
    • 32 Slot/48 Slot
      
    • MSB/LSB First Out
      
      
      
• System
  
  • Control of Read/Write Register through Serial/Parallel micom I/F
    
  • Generating output audio sampling clock by frequency synthesizer
    
  • Micom external DRAM DMA control function
    
  • Supports various RAM
    
    • SRAM/EDO/ Fast Page / Sync DRAM
      
    • EDO DRAM : 4M ~ 64M DRAM and 4 / 8 Bit Data Bus
      
    • Sync DRAM : 16M ~ 256M DRAM and 8 / 16 Bit Data Bus
      
    • SRAM : 4M/ 8M/ 16M SRAM and 8 / 16 Bit Data Bus